1. Technical Field of the Invention
The present invention relates to a method for coating a layer of reduced graphene oxide (rGO) onto the surface of substrate holes, especially the holes with high aspect ratio. In particular, the present invention relates to a wet coating process to produce a reduced graphene oxide layer on the surface of holes with high aspect ratio. The rGO layer may replace the barrier layer and seed layer in traditional semiconductor structure for decorating conductive metal (copper or Ti/TiN or Ta/TaN) in holes by electroplating process.
2. Description of the Prior Art
Based on the pursuit of miniaturization and microminiaturization for all kinds of electronic components, the 3D stack package technology is used to reduce the IC volume, and the vertical Through Silicon Via (TSV) and TSV metallization technology have been used to constitute the signaling pathways of 3D IC. TSV has a structure feature of high aspect ratio, which currently uses copper as metal material for having good conductivity. Chemical vapor deposition (CVD) method is used in most copper deposition technology.
In terms of structure and material properties, copper cannot form a self-protective film in the atmosphere, and is easily subject to oxidation and corrosion. Furthermore, copper has high diffusibility inside the crystalline silicon, which makes copper diffuse through SiO2 (insulating layer) into silicon active region, react with SiO2 and Si to form copper-silicon compounds, thus affecting the quality of the dielectric layer in a silicon wafer. To prevent this problem, a barrier layer is deposited on the wall of the hole in the TSV manufacturing process to isolate copper and silicon elements. Titanium nitride (TiN) and tantalum nitride (TaN) are typically used in traditional barrier layers. Since the resistivity of the barrier layer is still too high for the copper electroplating process, a thin and continuous layer of a seed layer must be deposited after the barrier layer. The functional role of the seed layer is to provide a conductive layer required for copper plating reaction and forming the nucleation layer of copper to ensure that the subsequent electroplated copper will completely fill in.
Even though the barrier layer and the seed layer can solve the problem of copper diffusion into silicon wafer and ensure the fill-in of electroplated copper, the silicon wafer using copper as the TSV conductive material still faces critical tests of mechanical strength, durability and reliability because of the material properties of copper and silicon. The main problem is the large difference in coefficient of thermal expansion of copper and silicon, 17.5×10−6/° C. for copper and 2.5×10−6/° C. for silicon. Therefore, thermo-mechanical stresses will be generated when electroplated copper is used in the TSV deep hole filling process. Particularly, thermo-mechanical stress occurs very quickly in the welding procedure of packaging process, leading to cracks between the internal dielectric layer and the Si substrate. To solve this problem, many studies and experiments have been conducted to find out new materials, such as nickel-tungsten alloy, to replace copper as the TSV conductive material of silicon wafer.
On the other hand, new materials can also be used as a diffusion barrier layer of copper material. It is known that the material properties of graphene make it suitable for using in the technique of semiconductor, touch panel or solar cell. WO 2013/096273 disclosed the use of graphene as a barrier layer for copper diffusion. The publication disclosed a chemical vapor deposition (CVD) method to deposit a layer of graphene on the surface of copper or nickel, and then transfer the formed product onto a desired substrate.
Based on the material properties of graphene and the disclosure of WO 2013/096273, the present invention proposes replacing the barrier layer and seed layer of TSV with a graphene layer. However, in the technique disclosed in WO 2013/096273 and the conventionally known CVD method, the graphene layer can only be deposited on a large substrate surface area, and cannot be deposited into the substrate hole with high aspect ratio. Therefore, it is essential to find out how to coat the graphene layer inside the holes of a substrate (particularly the holes with high aspect ratio).
The replacement of the barrier layer and seed layer of TSV with a graphene layer can efficiently simplify the TSV process and reduce its costs, and further achieve the purpose of producing the copper free conductive plug of TSV by a nickel-tungsten alloy to resolve problems arising from the copper filling. Based on this, the benefits of coating a graphene layer on the holes of high aspect ratio in the substrate are highly anticipated.